At Ubitium, we believe the best engineering happens when people with different perspectives tackle hard problems together. We welcome applicants from all backgrounds and experiences. What matters most is curiosity, skill, and the drive to build technology that improves the world. If that resonates with you, we’d love to hear from you. Our team members come from some of the best universities in the world and left some of the largest tech companies to build something truly remarkable.
Tasks
- Build cocotb-based testbenches for RTL blocks ranging from complicated datapaths to multilevel interconnect, driven by property-based test generation rather than fixed directed vectors.Write SystemVerilog Assertions (SVA) to catch protocol violations directly in simulation, plus cover property statements to close functional-coverage gaps.
- Cross-check RTL behavior against independent golden reference models (including formally-specified models) to catch divergence between spec intent and implementation
- Drive functional coverage closure, reviewing coverage reports
- Debug failures using waveform viewers and simulator transcripts, working from a failing assertion or model mismatch back to a root cause in the RTL, the testbench, or the model.
- Document and track open verification findings (RTL bugs, model gaps, or verification-methodology limitations) with clear reproduction steps, so issues are shareable and actionable across the team.
- Continuously improve the verification infrastructure itself (build flows, test harnesses, coverage tooling).
Requirements
- Languages: System Verilog, System Verilog Assertions, Python.
- Skills: RTL debugging, Property Based Verification, Git.
- Good to have: Formal Verification exposure.
Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.
Benefits
- A verification methodology you help shape, not just execute. The team builds its own property-based test harnesses, cross-checks RTL against formally-specified golden models, and wires up both SVA and native SystemVerilog covergroups. If you have opinions on how verification should be done, there’s real room to introduce them.
- Direct, tight feedback loops with the architects/designers. Findings get written up, discussed, and resolved collaboratively. You’ll see your root-cause analysis directly inform (or get corrected by) the people who wrote the RTL.
- Exposure across the full stack of a RISC-V SoC.
- Competitive salary plus stock options
- 30+ days of paid vacation
- Relocation support
- Full German social security and universal healthcare
- A modern office
- Free snacks, coffee, and drinks
- Work with people who actually know their stuff – computer architects, hardware nerds, and engineers who love tough problems.
- A culture where new ideas matter, but so does respect and collaboration.
- Space to grow: pick up new skills, dig into areas that interest you, and shape your own path.
- Get hands-on with real implementations of AI and signal processing – not just slides or buzzwords.
- An inclusive team where different perspectives are valued and everyone contributes.
We are constantly looking for talent. We recruit through multiple channels – friends & colleagues, universities and professors we know, recruiters, conventions, e-mails and LinkedIn. Join us today.
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