Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

Your tasks

At Synopsys, you will verify Interface IP that powers the semiconductor industry's most critical applications, and the team you work with will expect you to lead, not just execute.What You'll Be Doing

• Own end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff
• Build and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations
• Define verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios
• Develop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality
• Debug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators
• Collaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle
• Mentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices

The Impact You Will Have

• Your verification work will directly determine the quality and reliability of IP integrated into AI platforms, cloud infrastructure, and automotive systems used globally
• The testbenches and verification IP you build will be reused across multiple product generations, multiplying your impact across the organization
• Your coverage strategies and signoff criteria will set the standard for verification quality across the Interface IP portfolio
• The protocol bugs you catch pre-silicon will prevent costly respins and delays for customers building next-generation SoCs
• Your technical leadership will shape verification methodology improvements that raise the bar for the entire engineering team
• The mentorship you provide will accelerate the growth of engineers who will carry forward the verification practices you help establish
• Your collaboration with architecture and design teams will influence early design decisions that make verification more efficient and products more robust

Who You Are

The Team You'll Be Part OfYou will join a team of highly skilled verification engineers responsible for developing and verifying industry-leading Interface IP solutions. Working alongside experts in architecture, design, and verification, you will tackle some of the semiconductor industry's most challenging technical problems while contributing to products deployed worldwide. The team operates globally, collaborates across time zones, and values technical depth, ownership, and the kind of problem-solving that makes complex IP actually work in customer silicon.

Your profile

You AreYou have spent years verifying silicon that ships into data centers, AI accelerators, and high-performance systems where failure is not an option. The protocols you verify, PCIe, CXL, DDR, Ethernet, are not abstract specs to you. They are living, breathing systems with corner cases that only reveal themselves at 3 a.m. during a regression run, and you are the engineer who finds them before tape-out.You think in layers. You can debug a failing assertion in the UVM environment, trace it back to an RTL timing issue, and then connect it to a protocol compliance gap, all without losing the thread of what actually broke. When someone says "coverage is at 95%," you ask which 5% is missing and whether it matters.You do not wait for perfect documentation. Specs are incomplete, architectures evolve, and you have learned to work with what you have, ask the right questions, and build verification environments that adapt as the design matures. You have strong opinions on what makes a testbench reusable versus one that becomes technical debt, and you are not afraid to push back when a verification strategy does not account for real-world integration scenarios.

What You'll Need

• Bachelor's or Master's in Electrical Engineering or Computer Engineering with 8+ years of hands-on ASIC or SoC verification experience
• Deep expertise in SystemVerilog and UVM methodology, with a track record of building scalable verification environments from the ground up
• Strong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements
• Proven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff
• Solid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim
• Experience with verification IP development, assertion-based verification, or formal methods is a strong plus
• Knowledge of modern SoC architectures and high-speed communication interfaces is a plus
• You can walk into a spec review, identify the verification-critical corner cases that are not explicitly called out, and build a test plan that covers them
• When a regression fails at 2 a.m. before a milestone, you are the engineer who triages the root cause, determines if it is a real bug or a testbench issue, and has a fix ready by morning standup
• You know the difference between coverage that looks good on a dashboard and coverage that actually means the design is verified, and you are willing to have the hard conversation when the two do not align
• You can explain a complex protocol violation to a design engineer in a way that makes the fix obvious, and then turn around and present the same issue to an architect in terms of system-level impact
• You are comfortable leading technical discussions with senior engineers and architects, even when your point of view challenges the current plan
• You see mentorship as part of the job, not an extra task, and you make time to help less experienced engineers understand not just what to do, but why it matters

Rewards and Benefits

Date posted

Category EngineeringHire Type EmployeeJob ID 18402Remote Eligible NoDate Posted

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.