Verification Engineer

Requirements

• Languages: System Verilog, System Verilog Assertions, Python.
• Skills: RTL debugging, Property Based Verification, Git.
• Good to have: Formal Verification exposure.

Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.

Benefits

• A verification methodology you help shape, not just execute. The team builds its own property-based test harnesses, cross-checks RTL against formally-specified golden models, and wires up both SVA and native SystemVerilog covergroups. If you have opinions on how verification should be done, there’s real room to introduce them.
• Direct, tight feedback loops with the architects/designers. Findings get written up, discussed, and resolved collaboratively. You’ll see your root-cause analysis directly inform (or get corrected by) the people who wrote the RTL.
• Exposure across the full stack of a RISC-V SoC.
• Competitive salary plus stock options
• 30+ days of paid vacation
• Relocation support
• Full German social security and universal healthcare
• A modern office
• Free snacks, coffee, and drinks
• Work with people who actually know their stuff – computer architects, hardware nerds, and engineers who love tough problems.
• A culture where new ideas matter, but so does respect and collaboration.
• Space to grow: pick up new skills, dig into areas that interest you, and shape your own path.
• Get hands-on with real implementations of AI and signal processing – not just slides or buzzwords.
• An inclusive team where different perspectives are valued and everyone contributes.

We are constantly looking for talent. We recruit through multiple channels – friends & colleagues, universities and professors we know, recruiters, conventions, e-mails and LinkedIn. Join us today.

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Source: Statistisches Bundesamt (Destatis), table; dl-de/by-2-0; StarIn's calculation

Posted Nov 01, 2026

Posted Nov 01, 2026