Synthesis Engineer

At Ubitium, we believe the best engineering happens when people with different perspectives tackle hard problems together. We welcome applicants from all backgrounds and experiences. What matters most is curiosity, skill, and the drive to build technology that improves the world. If that resonates with you, we’d love to hear from you. Our team members come from some of the best universities in the world and left some of the largest tech companies to build something truly remarkable.

Tasks

Focus areas include but are not limited to: synthesis, STA, timing closure, place & route and/or sign-off. Prospective team members require strong Verilog/SystemVerilog; STA expertise; SDC; synthesis/STA tools preferred.

Requirements

Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.

Benefits

• Competitive salary plus stock options
• 30+ days of paid vacation
• Relocation support
• Full German social security and universal healthcare