Internship - Semiconductor Engineering

Depending on your area of assignment, the following are a plus:

• Digital: SystemVerilog, VHDL, UVM, SystemVerilog Assertions, or formal verification.
• Physical Design: Static Timing Analysis, CDC analysis, floorplanning/place-and-route, Cadence Innovus or Synopsys ICC2.
• Analog: SPICE simulation, Cadence Virtuoso, high-speed SerDes or PLL design.
• General: Python, Tcl, or Perl scripting; version-control systems and automated development flows.
• What We Offer
• Hands-on exposure to real semiconductor and connectivity projects, working closely with experienced engineering teams.
• The chance to apply your Master's coursework to real-world engineering tasks in an international environment.
• Flexible working hours with meaningful, independent responsibilities and hybrid options where applicable.
• Application

Please submit your CV and include the following information:

• Your Master's degree program, university, and expected graduation date.
• Proof of current enrollment.
• Preferred technical area of assignment and availability (hours per week).
• Relevant experience (projects, internships, EDA tools/languages) and earliest possible start date.

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